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MC10EP08, MC100EP08 3.3V / 5V ECL 2-Input Differential XOR/XNOR
The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation.
* 250 ps Typical Propagation Delay * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
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8 1 SO-8 D SUFFIX CASE 751 HEP08 ALYW 1 1 8 KEP08 ALYW
* * Safety Clamp on Inputs * Q Output Will Default LOW with Inputs Open or at VEE
8 1 TSSOP-8 DT SUFFIX CASE 948R
8 HP08 ALYW 1
8 KP08 ALYW 1
H = MC10 K = MC100 A = Assembly Location
L = Wafer Lot Y = Year W = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP08D MC10EP08DR2 MC100EP08D MC100EP08DR2 MC10EP08DT MC10EP08DTR2 MC100EP08DT Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel
MC100EP08DTR2 TSSOP-8
(c) Semiconductor Components Industries, LLC, 2001
1
April, 2001 - Rev. 3
Publication Order Number: MC10EP08/D
MC10EP08, MC100EP08
D0
1
8
VCC PIN
PIN DESCRIPTION
FUNCTION ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply
D0, D1, D0, D1 Q, Q D0 2 7 Q VCC VEE
TRUTH TABLE
D1 3 6 Q D0* L L H H D1* L H L H D0** H H L L D1** H L H L Q L H H L Q H L L H
D1
4
5
VEE
* Pins will default LOW when left open. ** Pins will default to VCC/2 when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 4 kV > 200 V > 2 kV Level 1 UL-94 code V-0 A 1/8" 28 to 34 135
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol VCC VEE VI Iout TA Tstg JA JC JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
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MC10EP08, MC100EP08
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4.) Output LOW Voltage (Note 4.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 5.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 2165 1365 2090 1365 2.0 Typ 28 2290 1490 Max 36 2415 1615 2415 1690 3.3 150 0.5 -150 Min 20 2230 1430 2155 1430 2.0 25C Typ 30 2355 1555 Max 38 2480 1680 2480 1755 3.3 150 0.5 -150 Min 20 2290 1490 2215 1490 2.0 85C Typ 32 2415 1615 Max 38 2540 1740 2540 1815 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 ohms to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7.) Output LOW Voltage (Note 7.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 8.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 3865 3065 3790 3065 2.0 Typ 28 3940 3190 Max 36 4115 3315 4115 3390 5.0 150 0.5 -150 Min 20 3930 3130 3855 3130 2.0 25C Typ 30 4055 3255 Max 38 4180 3380 4180 3455 5.0 150 0.5 -150 Min 20 3990 3190 3915 3190 2.0 85C Typ 32 4115 3315 Max 38 4240 3440 4240 3515 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 ohms to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10.) Output LOW Voltage (Note 10.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 11.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 -1135 -1935 -1210 -1935 VEE+2.0 Typ 28 -1010 -1810 Max 36 -885 -1685 -885 -1610 0.0 150 0.5 -150 Min 20 -1070 -1870 -1145 -1870 VEE+2.0 25C Typ 30 -945 -1745 Max 38 -820 -1620 -820 -1545 0.0 150 0.5 -150 Min 20 -1010 -1810 -1085 -1810 VEE+2.0 85C Typ 32 -885 -1685 Max 38 -760 -1560 -760 -1485 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 ohms to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP08, MC100EP08
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13.) Output LOW Voltage (Note 13.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 14.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 2155 1355 2075 1355 2.0 Typ 28 2280 1480 Max 36 2405 1605 2420 1675 3.3 150 0.5 -150 Min 20 2155 1355 2075 1355 2.0 25C Typ 30 2280 1480 Max 38 2405 1605 2420 1675 3.3 150 0.5 -150 Min 20 2155 1355 2075 1355 2.0 85C Typ 32 2280 1480 Max 40 2405 1605 2420 1675 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 ohms to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16.) Output LOW Voltage (Note 16.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 17.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 3855 3055 3775 3055 2.0 Typ 28 3980 3180 Max 36 4105 3305 4120 3375 5.0 150 0.5 -150 Min 20 3855 3055 3775 3055 2.0 25C Typ 30 3980 3180 Max 38 4105 3305 4120 3375 5.0 150 0.5 -150 Min 20 3855 3055 3775 3055 2.0 85C Typ 32 3980 3180 Max 40 4105 3305 4120 3375 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 ohms to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19.) Output LOW Voltage (Note 19.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 20.) Input HIGH Current Input LOW Current D D 0.5 -150 Min 20 -1145 -1945 -1225 -1945 VEE+2.0 Typ 28 -1020 -1820 Max 36 -895 -1695 -880 -1625 0.0 150 0.5 -150 Min 20 -1145 -1945 -1225 -1945 VEE+2.0 25C Typ 30 -1020 -1820 Max 38 -895 -1695 -880 -1625 0.0 150 0.5 -150 Min 20 -1145 -1945 -1225 -1945 VEE+2.0 85C Typ 32 -1020 -1820 Max 40 -895 -1695 -880 -1625 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 ohms to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP08, MC100EP08
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21.)
-40C Symbol fmax tPLH, tPHL tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 2. Fmax/JITTER) Propagation Delay to Output Differential D, D to Q, Q 170 Min Typ >3 Max Min 25C Typ >3 Max Min 85C Typ >3 Max Unit GHz ps 220 0.2 150 Q, Q 70 800 120 280 <1 1200 170 150 80 180 250 0.2 800 130 300 <1 1200 180 150 100 200 270 0.2 800 150 320 <1 1200 200 ps mV ps
Cycle-to-Cycle Jitter (See Figure 2. Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0
9 8 7 6 5 4 3 2 (JITTER) 3000 4000 5000 1 6000 JITTEROUT ps (RMS)
0
1000
2000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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EE EE
EEEEEEEE EEEEEEEE
MC10EP08, MC100EP08
Q Driver Device Qb 50 W 50 W
D Receiver Device Db
V TT V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP08, MC100EP08
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE W
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC10EP08, MC100EP08
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MC10EP08/D

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